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Abstract
The parallel architectures have been used widely for the solution of CPU and memory critical problems in the electronic CAD area. Due to several factors, such as the lack of efficient algorithms, the reduced portability of the code, and the cost of the hardware, the use is very limited. In this paper, we mainly present an effective Automatic Test pattern Generation (ATPG) system for large sequential circuits developed using the proposed portable Bulk Synchronous Parallel (BSP) model. The tool has been run on HP convex architectures. The experimental results are provided as well.